1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a ramp voltage generator and an image sensing device including the same.
2. Description of the Related Art
Image sensing devices capture images using photosensitive properties of semiconductors. Image sensing devices are often classified into charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. CMOS image sensors allow for both analog and digital control circuits to be directly realized on a single integrated circuit (IC), making CMOS image sensors the most widely used type of image sensor.
Electronic devices such mobile phones may be fabricated with built-in image sensing devices. The image sensing devices need to perform high speed operations to improve overall performance of the mobile apparatus. This has resulted in many specialized technologies being developed for image sensing devices. Particularly, technologies for reducing analog-to-digital converter (hereinafter, referred to as “ADC”) readout times of image sensing devices are being proposed.
For example, a 2-step ADC developed from a single-slope ADC has been proposed. The single-slope ADC requires a clock with a cycle of “210=1024” in order to output a digital signal of 10 bits, but the 2-step ADC requires a clock with a cycle of “23+27=136” by outputting 3 bits of the digital signal using a coarse clock and outputting the other 7 bits of the digital signal using a fine clock. Ideally, the readout time can be reduced by a ratio of “136/1024”. Since the coarse clock has a frequency lower than that of the fine clock in order to ensure the settling time of the coarse clock, the readout time is longer than the ideal readout time. However, the readout time of the 2-step ADC may be effectively reduced compared with the readout time of the single-slope ADC. In addition, since the 2-step ADC may be realized in a small area, it has been favored as a technology that can be applied to image sensing devices with a high number of pixels that operate at high speed.
The 2-step ADC uses a coarse ramp voltage corresponding to the coarse clock and a fine ramp voltage corresponding to the fine clock. For example, the 2-step ADC outputs a digital signal of 3 bits corresponding to a voltage level of a pixel signal, which is an analog signal, based on the coarse ramp voltage having a predetermined slope, and then outputs a digital signal of 7 bits corresponding to the voltage level of the pixel signal based on the fine ramp voltage having the predetermined slope. Typically, an image sensing device includes a ramp voltage generator for generating the coarse ramp voltage and the fine ramp voltage.
FIG. 1 illustrates an Internal configuration diagram of a ramp voltage generator.
Referring to FIG. 1, the ramp voltage generator includes a source current generation unit 11, a coarse ramp voltage generation unit 13, and a fine ramp voltage generation unit 15.
The source current generation unit 11 generates a first source current I1 in response to a first bias signal VNB, and generates a second bias signal VPB corresponding to the first source current I1.
For example, the source current generation unit 11 includes a first sinking section N1 and a first sourcing section P0. The first sinking section N1 is coupled between an output terminal of the second bias signal VPB and a ground voltage terminal VSS, and makes the first source current I1 sink to the ground voltage terminal VSS in response to the first bias signal VNB. For example, the first sinking section N1 includes a NMOS transistor having a gate coupled to an input terminal of the first bias signal VNB, and a drain and a source coupled between the output terminal of the second bias signal VPB and the ground voltage terminal VSS. The first sourcing section P0 is coupled between a power supply voltage terminal VDD and the output terminal of the second bias signal VPB, and makes the source current I1 sourced from the power supply voltage terminal VDD in response to the second bias signal VPB. For example, the first sourcing section P0 Includes a PMOS transistor having a gate and a drain coupled to the output terminal of the second bias signal VPB, and a source coupled to the power supply voltage terminal VDD.
The coarse ramp voltage generation unit 13 generates a first mirror current I2 varied by a coarse unit (for example, corresponding to 128 least significant bits (LSB)) in response to the second bias signal VPB and first to Xth coarse ramp control signals CR_CTRL<1:X>, and generates a coarse ramp voltage VCR based on the first mirror current I2.
For example, the coarse ramp voltage generation unit 13 includes a first mirroring section P1 to PX, a first switching section SW1 to SWX, and a first resistor section R_CR. The first mirroring section P1 to PX is coupled between the power supply voltage terminal VDD and first to Xth mirroring nodes MN1 to MNX, and resources the first mirror current I2 in response to the second bias signal VPB. For example, the first mirroring section P1 to PX includes first to Xth PMOS transistors respectively having gates coupled to an input terminal of the second bias signal VPB and sources and drains coupled between the power supply voltage terminal VDD and the first to Xth mirroring nodes MN1 to MNX. The first switching section SW1 to SWX is coupled between the first to Xth mirroring nodes MN1 to MNX and an output terminal of the coarse ramp voltage VCR, and generates the first mirror current I2 decreased by the coarse unit during a coarse conversion period in response to the first to Xth coarse ramp control signals CR_CTRL<1:X>. For example, the first switching section SW1 to SWX includes first to Xth switching elements which are sequentially open during the coarse conversion period in response to the first to Xth coarse ramp control signals CR_CTRL<1:X>. The first resistor section R_CR may be coupled between the output terminal of the coarse ramp voltage VCR and the ground voltage terminal VSS. For example, the first resistor section R_CR includes a resistance element.
The fine ramp voltage generation unit 15 generates a second mirror current I3 varied by a fine unit (for example, corresponding to 1 LSB) in response to the second bias signal VPB and first to Zth fine ramp control signals FR_CTRL<1:Z>, and generates a fine ramp voltage VFR based on the second mirror current I3.
For example, the fine ramp voltage generation unit 15 includes a second mirroring section PX+1 to PX+Z, a second switching section SWX+1 to SWX+Z, and a second resistor section R_FR. The second mirroring section PX+1 to PX+Z is coupled between the power supply voltage terminal VDD and (X+1)th to (X+Z)th mirroring nodes MNX+1 to MNX+Z, and resources the second mirror current I3 in response to the second bias signal VPB. For example, the second mirroring section PX+1 to PX+Z includes (X+1)th to (X+Z)th PMOS transistors respectively having gates coupled to the input terminal of the second bias signal VPB and sources and drains coupled between the power supply voltage terminal VDD and the (X+1)th to (X+Z)th mirroring nodes MNX+1 to MNX+Z. The second switching section SWX+1 to SWX+Z is coupled between the (X+1)th to (X+Z)th mirroring nodes MNX+1 to MNX+Z and an output terminal of the fine ramp voltage VFR, and generates the second mirror current I3 increased by the fine unit during a fine conversion period in response to the first to Zth fine ramp control signals FR_CTRL<1:Z>. For example, the second switching section SWX+1 to SWX+Z includes (X+1)th to (X+Z)th switching elements which are sequentially closed during fine conversion period in response to the first to Zth fine ramp control signals FR_CTRL<1:Z>. The second resistor section R_FR may be coupled between the output terminal of the fine ramp voltage VFR and the ground voltage terminal VSS. For example, the second resistor section R_FR includes a resistance element.
An image sensing device configured as above may have a mismatch between the coarse ramp voltage generation unit 13 and the fine ramp voltage generation unit 15. For example, a process mismatch occurs between the first to Xth PMOS transistors included in the first mirroring sections P1 to PX and the (X+1)th to (X+Z)th PMOS transistors included in the second mirroring sections PX+1 to PX+Z, or a process mismatch occurs between a load resistor of the coarse ramp voltage generation unit 13 and a load resistor of the fine ramp voltage generation unit 15.
For this reason, when a mismatch occurs between the coarse ramp voltage generation unit 13 and the fine ramp voltage generation unit 15, a mismatch also occurs between the coarse ramp voltage VCR and the fine ramp voltage VFR. In this case, a circuit using the coarse ramp voltage VCR and the fine ramp voltage VFR, for example, the 2-step ADC outputs a digital signal corresponding to a missing code. Graphs (A) and (B) of FIG. 2 illustrate the relation between the range of an analog signal (that is, ADC range) and a corresponding digital signal (i.e., count code) to which the 2-step ADC may convert the analog signal. For example, when the slope of the fine ramp voltage VFR is lower than that of the coarse ramp voltage VCR, a linearity error may occur as illustrated in graph (A) of FIG. 2. When the slope of the fine ramp voltage VFR is higher than that of the coarse ramp voltage VCR, a linearity error may occur as illustrated in graph (B) of FIG. 2.
Therefore, when the aforementioned linearity error occurs, the 2-step ADC outputs a digital signal corresponding to a missing code in converting an analog signal.